MAXQ7667AACM/V+T【PDF 22/40 页】IC MCU-BASED DAS 16BIT 48-LQFP

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MAXQ7667

16-Bit, RISC, Microcontroller-Based,

Ultrasonic Distance-Measuring System

______________________________________________________________________________________

the application code executes. The application codes

initiate reprogramming. If the password is not set, the

MAXQ7667 monitors the UART for an autobaud char-

acter (0x0D). If this character is received, the device

sets its serial baud rate and initiates a boot loader pro-

cedure. If 0x0D is not received after five seconds, the

device begins execution of the application code.

The following bootloader functions are supported:

Load

Dump

CRC

Verify

Erase

In-Application Programming

The in-application programming feature allows the C

to modify its own flash program memory while simulta-

neously executing its application software. This allows

on the fly software updates in mission-critical applica-

tions that cannot afford downtime. Erase and program

the flash memory using the flash programming func-

tions in the utility ROM. Refer to Section 18 of the

MAXQ7667 User’s Guide for a detailed description of

the utility ROM functions.

Stop Mode

Power consumption reaches its minimum in stop mode

(STOP = 1). In this mode, the external oscillator, inter-

nal RC oscillator, system clock, and all processing

halts. Trigger an enabled external interrupt input or

directly apply an external reset on

RESET to exit stop

mode. Upon exiting stop mode, the C either waits for

the external high-frequency crystal to complete its

warmup period or starts execution immediately from its

internal RC oscillator while the crystal warms up.

Interrupts

Multiple interrupt sources quickly respond to internal

and external events. The MAXQ architecture uses a

single interrupt vector (IV) and single interrupt-service

routine (ISR) design. Enable interrupts globally,

individually, or by module. When an interrupt condition

occurs, its individual flag is set even if the interrupt

source is disabled at the local, module, or global level.

Clear interrupt flags within the interrupt routine to avoid

repeated false interrupts from the same source.

Provide an adequate delay between the write to the

flag and the RETI instruction using application software

to allow time for the interrupt hardware to remove the

internal interrupt condition. Asynchronous interrupt

flags require a one-instruction delay and synchronous

interrupt flags require a two-instruction delay.

When an enabled interrupt is detected, software jumps

to a user-programmable interrupt vector location. The

IV register defaults to 0000h on reset or power-up.

Once software control transfers to the ISR, use the

interrupt identification register (IIR) to determine if the

source of the interrupt is a system register or peripheral

interrupt source. The following interrupt sources are

available:

Watchdog interrupt

External interrupts 0–7 on port 0 and port 1

Timer 0 low compare, low overflow, capture/com-

pare, and overflow interrupts

Timer 1 low compare, low overflow, capture/com-

pare, and overflow interrupts

Timer 2 low compare, low overflow, and overflow

interrupts

Schedule timer alarm interrupt

SPI data transfer complete, mode fault, write colli-

sion and receive overrun interrupts

UART transmit, receive interrupts

LIN mode master or slave interrupt

SAR ADC data ready interrupt

Echo envelope LPF output, FIFO full, and com-

parator interrupts

Digital and I/O voltage brownout interrupts

High-frequency oscillator failure interrupt

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